1. Field of the Invention
The present invention relates to a CMOS image sensor and a method of fabricating the same, which can reduce an area of a contact region so that the CMOS image sensor is highly integrated.
2. Description of the Related Art
Generally, an image sensor is a semiconductor device to convert an optical image into electric signal. A charge coupled device (CCD) includes metal-oxide-silicon (MOS) capacitors located at very close positions, and stores and transfers charge carriers to the MOS capacitors. On the other hand, a complementary MOS (CMOS) image sensor includes a control circuit and a signal processing circuit as a peripheral circuit. In the CMOS image sensor, MOS transistors are formed as many as pixels by using CMOS technology. The CMOS image sensor sequentially detects output data through the switching operations of the MOS transistors.
In fabricating various kinds of image sensors, many attempts to increase photosensitivity have been made. One of them is a light concentrating technology. Because the CMOS image sensor includes a photodiode for detecting light and a CMOS logic circuit part for processing the detected light to output an electric signal, the photodiode is formed to occupy much area in the entire area of the CMOS image sensor so as to increase photosensitivity.
A CMOS image sensor according to the related art will be described below with reference to FIGS. 1 to 3.
FIG. 1 is a plan view of the CMOS image sensor according to the related art, FIG. 2 is a sectional view taken along line II-II′ of FIG. 1, and FIG. 3 is a sectional view taken along III-III′ of FIG. 1.
Referring to FIG. 1, a photodiode (hereinafter, referred to as a PD) is formed in a substrate (not shown), and a floating diffusion (hereinafter, referred to as an FD) region is formed at a position spaced apart from the PD. A first gate 200a overlaps one end of the PD, and a second gate 200b overlaps one end of the FD region. The first gate 200a and the second gate 200b transfer an optical signal from the PD to the FD region by on-off operations. A third gate 200c is connected to the FD region and acts as a source follower buffer amplifier. For example, the first gate 200a is a transfer gate and the second gate 200b is a reset gate, and the third gate 200c is a drive gate and a line connected to a source or drain of a reset transistor. Although not shown in FIG. 1, the CMOS image sensor further includes a fourth gate, that is, a select gate, which can perform addressing through a switching operation.
In addition, the CMOS image sensor according to the related art includes a first contact 310 and a second contact 320. The first contact 310 and the second contact 320 are connected to the FD region and the third gate 200c, respectively. Furthermore, the first contact 310 and the second contact 320 are connected to each other through a metallic wiring line 400, so that the third gate 200c and the FD region are connected to each other. FIG. 1 illustrates the state when the process of forming the first contact 310 and the second contact 320 is completed so as to connect the FD region to the third gate 200c. The FD region is a highly doped n-type (n+) and is formed through an ion implantation process for the formation of the PD.
Referring to FIGS. 2 and 3, a device isolation layer 110 is locally formed on the substrate 100, and the PD is formed in a predetermined portion of the substrate 100 adjacent to the device isolation layer 110 through an ion implantation process. The substrate 100 is formed using a semiconductor layer. For simplicity of the drawings, such a substrate is referred to as the substrate 100. In addition, an n-type photodiode region (hereinafter, referred to as an n-region) is formed in a lower portion of the p-type substrate, and a p-type photodiode region (hereinafter, referred to as P0) is extended from a surface of the substrate 100 toward the n-region.
The first gate 200a and the second gate 200b have a stacked structure of a gate dielectric layer 210 and a gate electrode 220 on the substrate 100. The first gate 200a and the second gate 200b are formed to overlap one end of the PD and one end of the FD region, respectively. The third gate 200c is formed on the device isolation layer 110 adjacent to the FD region. The third gate 200c has a stacked structure of the gate dielectric layer 210 and the gate electrode 220. Spacers 230 are formed of an insulating layer on sidewalls of the first, second and third gates 200a, 200b and 200c. The gate electrode 220 may have a single layer structure of polysilicon layer, or a multi-layer structure where polysilicon layer and tungsten layer are sequentially stacked.
An insulating layer 120 is formed on the resulting structure where the third gate 200c and the FD region are formed. The first contact 310 and the second contact 320, passing through the insulating layer 120, are connected to an upper surface of the gate electrode 220 of the third gate 200c and an upper surface of the FD region, respectively. The first contact 310 and the second contact 320 are connected through the metallic wiring line 400 formed on the insulating layer 120. That is, the third gate 200c and the FD region are electrically connected by the metallic wiring line 400 connecting the first contact 310 to the second contact 320. The third gate 200c can receive the optical signal of the FD region, which is transferred from the PD, and amplifies the received optical signal through the third gate 200c. 
In the CMOS image sensor according to the related art, the PD region can be defined after the first contact region, the second contact region, and the metal line region are secured in the CMOS logic circuit part, in order to electrically connect the FD region and the third gate.
In order to increase photosensitivity, an area ratio of the PD, not the CMOS logic circuit part, has to be large in the entire area of the CMOS image sensor. Therefore, there is a limitation in reducing an entire size of the image sensor. Consequently, there is a limitation in improving the photosensitivity.